This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-71606, filed Mar. 17, 1999; and No. 11-335441, filed Nov. 26, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor integrated circuit, and in particular, to a clock synchronization semiconductor integrated circuit for use, for example, in a semiconductor memory such as a clock synchronization DRAM or ROM which has an operation mode for allowing the circuit to internally and continuously serially transfer multi-bit data.
In recent years, the wiring length of semiconductor memories has been increased linearly with the chip size. In addition, the use of finer elements has been contributing to reduction in wiring width and interval. As a result, the wiring resistance and capacity have increased, and the adverse effect of a possible wiring delay on the overall operation speed performance is growing.
Due to its wiring length over which signals are transmitted, a portion of a chip located far away from I/O pads and a control circuit (for example, a peripheral portion of the chip) is more significantly affected by a possible wiring delay than a portion thereof located closer to the input pads and control circuit (for example, a central portion of the chip). As a result, reading data from cell array blocks in the chip peripheral portion requires a larger amount of time than reading data from cell array blocks in the chip central portion.
Some clock synchronization DRAMs have an operation mode or an output data transfer system for loading, in a transfer block, data read out from a plurality of cell array blocks arranged on a chip so that the output data of multiple bits loaded in this transfer block are continuously transferred bit by bit to an output buffer in synchronism with a clock synchronization signal.
The time required to access the plurality of cell array blocks depends on the wiring length of an address signal line between an address buffer and an address decoder for each of the cell array blocks. With conventional on-chip arrangements, accesses to the cell array blocks in the chip peripheral portion require a larger amount of time than accesses to the cell array blocks in the chip central portion.
In the conventional clock synchronization DRAM, however, data read out from the cell array blocks in the chip peripheral portion are loaded in the transfer block simultaneously with data read out from the cell array blocks in the chip central portion.
This is disadvantageous in that only a small timing margin is available in loading, in the transfer block, data read out from the cell array blocks in the chip peripheral portion, which may be caused by an access delay, whereby data transfers from the cell array blocks in the chip peripheral portion may determine the timings for all the cell array blocks. In particular, when data being read out from a cell array block in the chip peripheral portion, which may be subjected to an access delay, the data is to be loaded in the transfer block and if this data has not reached the transfer block yet at the loading timing, then loading of this data may fail.
The above conventional problem will be described below in detail with reference to FIGS. 1, 2, and 3A-3I.
FIG. 1 shows an example of a configuration of part of a conventional clock synchronization DRAM, particularly, of its memory cell arrays and other parts related to output data transfers.
In FIG. 1, the memory cell arrays are divided into a plurality of (in this example, four) cell array blocks (each including a sense amplifier) 101 to 104, and include a row decoder 11 shared by each of the cell array blocks 101 to 104 and column decoders 121 to 124 corresponding to the cell array blocks 101 to 104, respectively.
An address signal is input to an address buffer 13, a row address signal is supplied to the row decoder 11, and a column address signal is supplied to each of the column decoder 121 to 124.
Data read out from a memory cell in each cell array block 101 to 104 and corresponding to the row and column address signals is stored in a corresponding one of four data line buffers (DQ Buffers) 141 to 144.
Data DQdata1 to DQdata4 stored in the data line buffers 141 to 144, respectively, are input to a data transfer block 16 through data lines 151 to 154, respectively, and from the data transfer block 16, the data are output in a predetermined order in synchronism with a control clock CLK. The data are further output to an output buffer (Dout Buffer) 18 through an output signal line 17.
In the arrangement of the cell array blocks 101 to 104, the cell array block 101 is located closer to a chip peripheral portion than the cell array block 104, and due to the locational relationship between the address buffer 13 and the cell array blocks 101 to 104, the wiring for each column address signal is relatively long and the lengths of the wirings for column address signals between the address buffer 13 and each of the column decoders 121 to 124 vary.
FIG. 2 shows a conventional example of the data transfer block 16 in FIG. 1.
The four bit data DQdata1 to DQdata4 read out in parallel from the four cell array blocks and stored in the corresponding data line buffers are stored in first to final registers 71 to 74, respectively, of a shift register in response to the control clock CLK. The data datal to data4 stored in the first to final registers 71 to 74 are transferred in synchronism with a falling edge of the control clock CLK, and output data Dout data from the final register 74 is output to the output buffer 18 in FIG. 1.
FIGS. 3A to 3I are timing charts showing an example of an operation of the shift register in FIG. 2.
At a rising edge of the control clock CLK, the data datal in the first stage register 71 is transferred to the second stage register 72 as shift data shiftdatal, the data data2 in the second register 72 is transferred to the third register 73 as shift data shiftdata2, and the data data3 in the third stage register 73 is transferred to the final stage register 74 as shift data shiftdata3. The shift data data4 in the final stage register 74 changes to the output data Dout data. Likewise, at each rising edge of the sequentially supplied control clock CLK, data is shifted and then transferred. Then, the bit data data4, data3, data2, datal are sequentially output as the output data Dout data.
In this manner, of the data DQdata1 to DQdata4 input to the data transfer block, the data DQdata1, which is output from the cell array block 101 in the chip peripheral portion, takes effect as the output data Dout data last.
On the other hand, the data DQdata1 to DQdata4 input to the data transfer block are each loaded at the same rising edge of the control clock CLK, that is, these data each use the same loading timing.
Thus, the data DQdata1, which is output from the cell array block 101 in the chip peripheral portion, has the smallest loading timing margin.
In FIG. 1, operational timings for the transfer block 16 will be considered by assuming that a significant signal delay occur in word lines in the cell array blocks 101 to 104, which are selectively driven by the row decoder 11, and that the amount of time required for the data DQdata1 output from the cell array block 101 in the chip peripheral portion to reach the data line buffer 131 substantially differs from the amount of time required for the data DQdata4 output from the cell array block 104 in the chip central portion to reach the data line buffer 144.
In this case, a data loading period T following a certain rising edge of the control clock CLK is considered. As shown in FIGS. 3A to 3E, of the data DQdata1 to DQdata4 input to the data transfer block 16, the DQdata2 to DQdata4 are loaded in the registers 72, 73, 74, respectively, as shown in FIGS. 3G to 3I. The data DQdata1, which has been output from the cell array block 101 in the furthest chip peripheral portion, has not reached the register 71 yet, as shown in FIG. 3B. Consequently, this data DQdata1 cannot be loaded in the register 71, thereby preventing the correct output from being provided for the data transfer block 16 as the output data Dout data.
As described above, a possible signal delay forces the data transfer block, which is shown in FIG. 2, to use a small timing margin in loading the data output from the cell array block 101 in the chip peripheral portion. As a result, a long signal delay in the word lines may preclude the output of the data from the cell array block 101 in the chip peripheral portion.
The above conventional examples in FIGS. 1 and 2 have been described in conjunction with the disadvantage arising from the difference in access time between memory cell arrays located close to the address buffer 13 and memory cell arrays located far away therefrom. However, an output data path leading from each of the memory cell arrays to the output buffer may also be a disadvantage. That is, the data may not be output correctly due to the difference in distance between each of the memory cell arrays and the output buffer. This may occur when long output signal lines must be wired, and may cause a significant signal delay, which in turn induces, for example, delayed data outputs or obtuse output waveforms.
In addition to the above read-out delay problem, a major recent problem of semiconductor integrated circuits, particularly semiconductor memories is noise in a power line originating in a temporary increase in power consumption. In particular, in a clock synchronization semiconductor memory operating clock synchronization with an external clock, a large number of circuits may operate simultaneously with the same timing, causing a high current to temporarily flow through the power line.
The chip includes, for example, a plurality of data line buffer circuits providing an I/O data transfer function; however, since the same signal is used to activate these buffer circuits, the plurality of data line buffer circuits simultaneously consume power, resulting in the flow of a high peak current.
Accommodating this high peak current requires an internal power supply with a high driving capability and a wide power line. Thus, the number of circuits and the area of the chip must be increased.
The present invention is provided to solve the above problems, and it is an object thereof is to provide a semiconductor integrated circuit that increases a timing margin for loading of output data from those of a plurality of circuit blocks outputting data in parallel that are subject to a long delay in control signal transfer, in order to prevent the transfer of data output from these circuit blocks from determining timings for all data output from each circuit block, thereby enabling data output from each circuit block to be reliably obtained.
In addition, the present invention is provided in view of the above circumstances, and it is an object thereof to reduce a peak current occurring during an I/O data transfer in order to reduce the area of a chip in the semiconductor integrated circuit.
A first aspect of the present invention provides a semiconductor integrated circuit comprising a first to an n-th data lines through which data read from n (n is a positive integer) cell array blocks are transmitted, a data selector having a plurality of selectors to which at least two of the data on the first to n-th data lines are input, for selecting and outputting the n data read out to the first to n-th data lines from the n cell array blocks, in the order in which the data were read out from the n cell array blocks, an output buffer to which an output from the data selector is transmitted via an output signal line, and a selector control circuit for controlling and switching the selection operation of the data selector based on a control clock.
A semiconductor integrated circuit according to a second aspect of the present invention is the first semiconductor integrated circuit wherein the data selector selects one of the n data read out to the first to n-th data lines from the n cell array blocks that was read out first from the corresponding cell array block and then sequentially selects and outputs the remaining data in synchronism with a first to an n-th selection signals in the order in which these data were read out from the corresponding cell array blocks.
A semiconductor integrated circuit according to a third aspect of the present invention is the second semiconductor integrated circuit wherein the data selector comprises an i-th selector controlled to select one of the data input through the first and second lines that was read out earlier from the corresponding cell array block and then to select the other data based on a first selection signal, and (nxe2x88x922) (i+1) selectors controlled to select one of the output data from the i-th (i=1 to nxe2x88x922) selector and data input through an (i+2) data line that was read out earlier from the corresponding cell array block and then to correspondingly select the other data based on a second to an (nxe2x88x921)-th selection signals.
A semiconductor integrated circuit according to a fourth aspect of the present invention is the second or third semiconductor integrated circuit wherein the first selection signal and the second to (nxe2x88x921)-th selection signals have their logic level reversed in synchronism with control clock signals in the order from the (n+1) to first selection signals, and wherein the data selector selects and outputs the data in the order from the data on the n-th data line to the data on the first data line.
Further aspect of a semiconductor integrated circuit according to the present invention comprises a first and a second data lines for transmitting data, a first and a second data line buffer circuits connected to the first and second data lines, respectively, and a first and a second data line buffer control circuits for activating the first and second data line buffer circuits, respectively, wherein the first data line buffer control circuit has a delay time different from a delay time in the second data line buffer control circuit.
In addition, the semiconductor integrated circuit desirably includes the following features:
The semiconductor integrated circuit is characterized by further comprising first and second data selectors to which data is transmitted from the first and second data line buffer circuits, respectively, and in that the first data selector performs the selection operation with timings different from those for the second data selector.
The semiconductor integrated circuit is characterized in that the first data line buffer circuit is activated later than the second data line buffer circuit, and in that the first data selector performs the selection operation later than the second data selector.
The semiconductor integrated circuit is characterized in that the first and second data selectors each comprise shift registers, and in that the first data selector performs the selection operation in response to a clock signal issued later than that for the second data selector.
The semiconductor integrated circuit is characterized in that the first data line buffer control circuit has the same configuration as the second data line buffer control circuit but further includes a delay element.
The semiconductor integrated circuit is characterized in that the first data line buffer circuit is activated later than the second line buffer circuit.
With the above configuration, the present invention reduces a peak current during an I/O data transfer and also reduces the area of a chip in the semiconductor integrated circuit.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.